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16com/40seg dot matr ix lcd controller & driver S6A0072 1 introduction S6A0072 is a dot matrix lcd driver & controller ic which is fabricated by low power cmos technology. it is capable of displaying 1 - line 16 characters or 2 - line 8 characters with 5 8 dots format. functions char acter type dot matrix lcd driver & controller easy interface with 4 - bit or 8 - bit mpu. internal driver: 16 common and 40 segment signal output. display charac ter pattern: 5 8 dots format (240 kinds) direct programming of the special character patterns by character generator ram mask option for programming custom er character patterns various instruction functions automatic power on reset features internal memory - character generator rom (cgrom): 9600 bits (240 chara cters 5 8 dot) - character generator ram (cgram): 160 bits (4 characters 5 8 dot) - display data ram (ddram): 128 bits (16 c haracters 8bits) low power operation - power supply voltage range: 2.7 to 5.5v (vdd) - lcd drive voltage range: 3.0 to 11.0 (vdd - v5) cmos process duty cycle: 1/16 built - in oscillator low power consumption internal divide resistor for lcd driving voltage cog available
S6A0072 16com/40seg dot m atrix lcd controller & driver 2 block diagram power on reset (por) input buffer instruction register (ir) instruction decoder address counter display data ram (ddram) 16 x 8-bit timing generator oscillator test data register (dr) character generator ram (cgram) 32 bytes character generator rom (cgrom) 9600 bits cursor blink control circuit 40-bit shift register 40-bit latch circuit segment driver 16-bit shift register common driver c1-c16 s1-s40 parallel to serial converter reset db0-db7 rs r/w vdd gnd(vss) 8 8 8 8 8 8 8 e extclk ext_int vdd v1 v2 v3 v5 v4
16com/40seg dot matr ix lcd controller & driver S6A0072 3 pad diagram S6A0072 c16 c15 c14 c13 c12 c11 c10 c9 test dummy dummy dummy s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 s32 s33 s34 s35 s36 s37 s38 s39 s40 dummy dummy dummy (0, 0) x y c8 c7 c6 c5 c4 c3 c2 c1 db7 db6 db5 db4 vdd vdd vdd vss vss vss v5 v5 v5 v3 v2 reset rs e db1 db2 db3 db0 r/w dummy dummy extclk ext_int S6A0072 chip size: 7600 2160 m m pad pitch: min. 125 m m chip thickness 675 m m al pad specifications al pad size on y side: 87 94 m m al pad size on x side: 94 87 m m au bump specifications bump size on y side: 77 84 m m bump size on x side: 84 77 m m bump height: 18 1 m m
S6A0072 16com/40seg dot m atrix lcd controller & driver 4 pad center coordinat es unit: um pad no. pad name coordinate pad no. pad name coordinate pad no. pad name coo rdinate x y x y x y 1 dummy - 3642 - 881 31 c3 3643 64 61 s24 - 455 923 2 dummy - 3032 - 881 32 c4 3643 189 62 s25 - 580 923 3 extclk - 2632 - 881 33 c5 3643 314 63 s26 - 705 923 4 ext_int - 2232 - 881 34 c6 3643 439 64 s27 - 830 923 5 vss - 1832 - 881 35 c7 3643 564 65 s28 - 955 923 6 vss - 1707 - 881 36 c8 3643 689 66 s29 - 1080 923 7 vss - 1582 - 881 37 dummy 3643 923 67 s30 - 1205 923 8 vdd - 1182 - 881 38 s1 2464 923 68 s31 - 1330 923 9 vdd - 1057 - 881 39 s2 2329 923 69 s32 - 1455 923 10 vdd - 932 - 881 40 s3 220 4 923 70 s33 - 1580 923 11 v5 - 532 - 881 41 s4 2079 923 71 s34 - 1705 923 12 v5 - 407 - 881 42 s5 195 4 923 72 s35 - 1830 923 13 v5 - 282 - 881 43 s6 1829 923 73 s36 - 1955 923 14 v3 117 - 881 44 s7 1704 923 74 s37 - 2080 923 15 v2 517 - 881 45 s8 1579 923 75 s38 - 2205 923 16 resetb 917 - 881 46 s9 1454 923 76 s39 - 2330 923 17 rs 1317 - 881 47 s10 1329 923 77 s40 - 2463 923 18 r/w 1717 - 881 48 s11 1204 923 78 dummy - 3642 923 19 e 2117 - 881 49 s12 1079 923 79 c16 - 3643 689 20 db0 2521 - 881 50 s13 954 923 80 c15 - 3 643 564 21 db1 2697 - 881 51 s14 829 923 81 c14 - 3643 439 22 db2 2871 - 881 52 s15 704 923 82 c13 - 3643 314 23 db3 3047 - 881 53 s16 579 923 83 c12 - 3643 189 24 dummy 3643 - 881 54 s17 454 923 84 c11 - 3643 64 25 db4 3643 - 717 55 s18 329 923 85 c10 - 3643 - 60 26 db5 3643 - 591 56 s19 204 923 86 c9 - 3643 - 184 27 db6 3643 - 467 57 s20 71 923 87 test - 3643 - 341 28 db7 3643 - 341 58 s21 - 70 923 88 dummy - 3643 - 467 29 c1 3643 - 184 59 s22 - 205 923 89 dummy - 3643 - 592 30 c2 3643 - 60 60 s23 - 330 923 90 dummy - 3643 - 717
16com/40seg dot matr ix lcd controller & driver S6A0072 5 pin description pin input/output name description interface vdd power power supply & lcd bias pin for logical circuit (+3v, +5v) power supply vss (gnd) 0v (gnd) v2, v3, v5 bias voltage level for lcd driving s1 - s40 output segment outpu t segment signal output for lcd driving lcd c1 - c16 input common output common signal output for lcd driving lcd extclk input external clock input when using external clock, used as clock input pin. when using internal oscillator, connect to vdd or vss. external clock ext_int input external/internal oscillator clock select when ext_int = "high", external clock is used. when "low", internal oscillator is used. vdd/vss rs input register select used as register selection input. when rs = "high", data re gister is selected. when rs = "low", instruction register is selected. mpu r/w input read/write used as read/write selection input. when r/w = "high", read operation. when r/w = "low", write operation. e input read/write enable used as read/write enab le signal. db0 - db3 input/output data bus 0 - 7 when 8 - bit bus mode, used as low order bi - directional data bus. during 4 - bit bus mode open these pins. db4 - db7 when 8 - bit bus mode, used as high order bi - directional data bus. in case of 4 - bit bus mode, used as both high and low order. db7 is used for busy flag output during read instruction operation. resetb input reset if it is necessary to initialize the system by hardware, force "low", level signal to this terminal about 1.2ms. test output test p in internal oscillator test pin. open this pin. open
S6A0072 16com/40seg dot m atrix lcd controller & driver 6 function description system interface this chip consists of two kinds of interface type with mpu: 4 - bit bus and 8 - bit bus. 4 - bit bus and 8 - bit bus is selected by dl bit of function set in the instructi on register. during read or write operation, two 8 - bit registers are used. one is the data register (dr), the other is the instruction register (ir). the data register (dr) is used as a temporary data storage place for being written into or read from ddram /cgram, target ram is selected by ram address setting instruction. each internal operation, reading from or writing into ram, is done automatically. thus, after mpu reads dr data, the data in the next ddram/cgram address is transferred into dr automaticall y. also after mpu writes data to dr, the data in dr is transferred into ddram/cgram automatically. the instruction register (ir) is used only to store instruction code transferred from mpu. mpu cannot read data from instruction register. the register selec tion depends on rs input pin setting in both 4 - bit bus mode. table 1. various kinds of operations according to rs and r/w bits rs r/w operation 0 0 instruction write operation (mpu writes instruction code into ir) 0 1 read busy flag (db7) and address co unter (db0 - db6) 1 0 data write operation (mpu writes data into dr) 1 1 data read operation (mpu reads data from dr) busy flag (bf) bf = "high" indicates that the internal operation is being processed. so during this time the next instruction cannot b e accepted. bf can be read, when rs = low and r/w = high (read instruction operation), through db7 port. before executing the next instruction, be sure that bf is not high. address counter (ac) address counter (ac) stores the address of ddram/cgram that a re transferred from ir. after writing into (reading from) ddram/cgram data, ac is increased (decreased) by 1 automatically. when rs = "low", and r/w = "high", ac value can be read through db0 - db6 ports.
16com/40seg dot matr ix lcd controller & driver S6A0072 7 display data ram (dd ram) ddram stores 8bits char acter code in cgrom/cgram and its maximum number is 16 (16 characters). ddram address is set by the address counter (ac) as hexadecimal number. ac6 ac5 ac4 ac3 ac2 ac1 ac0 msb lsb hex hex the relations of ddram address and display position is as follows . 1) ddram addressing mode 0 (a = 0) - in this addressing mode, the address range of ddram is 00h - 0fh. 00 01 02 03 04 1 2 3 4 5 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 0f 16 00 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 0b 0c 0d 6 7 8 9 10 11 12 13 14 15 05 06 07 08 09 0a 0e 16 0f 00 com1 - com8 com9 - com16 display position ddram address after shift left: after shift right: 2) ddram addressing mode 1 (a = 1) in this addressing mode, the address range of ddram is 00h - 07h and 40h - 47h. 00 01 02 03 04 1 2 3 4 5 43 44 45 6 7 8 9 10 11 12 13 14 15 05 06 07 40 41 42 46 47 16 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 6 7 8 9 10 11 12 13 14 15 05 06 07 40 16 com9 com16 01 02 03 04 1 2 3 4 5 com1 com8 6 7 8 9 10 11 12 13 14 15 05 06 16 4f 00 com1 - com8 com9 - com16 display position ddram address after shift left: after shift right: 43 44 45 41 42 46 47 00 43 44 45 41 42 46 40 07
S6A0072 16com/40seg dot m atrix lcd controller & driver 8 chara cter generator ram ( cgram) cgram is used for user defined character pattern. the format of the character pattern is 5 7 dots except for the cursor position and has a maximum of 4 characters. to use the character pattern in cgram write the character code into ddram as shown in table 2. table 2. relationship between character code (ddram) and character pattern (cgram) 1 1 0 1 1 1 1 1 0 d7 d6 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 character code (ddram data) cgram address cgram data pattern number 0 0 * 0 * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 . . 0 0 0 * 0 * 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 x x x 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pattern 1 x x x 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . pattern 4 . . . . . . . . . . . . . . . . . . . cursor position cursor position 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 note : " * " don?t care.
16com/40seg dot matr ix lcd controller & driver S6A0072 9 character generator rom (cgrom) cgrom generates 5 8 character pattern from character generate code in ddram. cgrom has 5 8 - dot 240 character pattern including cursor position . if the data in cursor position bit are high, the data are included to the character pattern. so, the selected positions are always "on" regardless to cursor position. the relationship between character code and character pattern can be referred to table 5. timing generation ci rcuit timing generation circuit generates clock signals for the internal operations. lcd driver circuit lcd driver circuit has 16 common and 40 segment output signals for lcd driving. data from cgram/cgrom is transferred to 40 - bit s egment shift register serially, then it is stored to 40 - bit segment output latch. when each com is selected by a 16 - bit common register, the segment data also outputs through segment driver from 40 - bit segment output latch. cursor/blink control circuit it controls cursor/blink on/off at the cursor position.
S6A0072 16com/40seg dot m atrix lcd controller & driver 10 instruction descript ion outline to overcome the speed difference between the internal clock of S6A0072 and the mpu clock, the S6A0072 performs an internal operation by storing control information to ir or dr. the internal operation is determined according to the signal from mpu, composed of read/write and data bus. instruction can be divided into four types: S6A0072 function set instructions (set display methods, set data length, etc.) address set instructions to internal ram data transfer instructions with internal ram others. the address of internal ram is automatically inc reased or decreased by 1. note: during an internal operation, the busy flag (db7) is high. busy flag check must precede the next instruction. when an mpu program with busy flag (db7) checking is made, 1/2fosc is necessary for execu ting the next instruction by the falling edge of the "e" signal after the busy flag (db7) goes to "low".
16com/40seg dot matr ix lcd controller & driver S6A0072 11 table 3. instruction table instruction instruction code description execution time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) test mode 0 0 0 0 0 0 0 0 0 0 device test mode (when 4 - bit interface mode) no operation (when 8 - bit interface mode) - clear display 0 0 0 0 0 0 0 0 0 1 write " 20h " to ddram and set ddram address to " 00h " from ac. 6 31 m s return home 0 0 0 0 0 0 0 0 1 * set ddram address to " 00h " from ac and return cursor to its origi nal position if shifted. the contents of ddram are not changed. 6 31 m s entry mode set 0 0 0 0 0 0 0 1 i/d s assign cursor movi ng direction and enable entire display shift. 3 9 m s display on/off control 0 0 0 0 0 0 1 d c b all display (d), cursor (c), and blinking of cursor position character on/off control bit (b). 3 9 m s cursor or display shift 0 0 0 0 0 1 s/c r/l * * cursor and display shift and their direction con trol without changing ddram data. 3 9 m s function set 0 0 0 0 1 dl a * m1 m0 set interface data length (dl), ddram addressing mode (a) and com/seg output pattern (m0, m1). 3 9 m s set cgram address 0 0 0 1 * ac4 ac3 ac2 ac1 ac0 set cgram address in address counter. 3 9 m s set ddram address 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address in address counter. 3 9 m s read busy flag and ddram 0 1 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 whether in internal operation or not can be known by reading bf. the contents of address counter can also be 0 m s add - ress cgram * * ac4 ac3 ac2 ac1 ac0 read note: ? * ? don ? t care.
S6A0072 16com/40seg dot m atrix lcd controller & driver 12 table 3. instruction table (continued) instruction instruction code description execution time rs r/w db7 db6 db5 db4 db3 db2 db1 db0 (fosc = 270khz) write d ata to ram ddram 1 0 d7 d6 d5 d4 d3 d2 d1 d0 write data into internal ram (ddram/cgram). 43 m s cgram * * * d4 d3 d2 d1 d0 read data from ram ddram 1 1 d7 d6 d5 d4 d3 d2 d1 d0 read data from internal ram (ddram/cgram). 4 3 m s cgram * * * d4 d3 d2 d1 d0 note: ? * ? don ? t care. i/d = 1: increment, i/d = 0: decrement s = 1: shift enable, s = 0: shift disable s/c = 1: display shift, s/c = 0: move cursor r/l = 1: shift right, r/l = 0: shift left dl = 1: 8 - bit interface, dl = 0: 4 - bit interface a = 0: ddram addressing mode 0, a = 1: ddram addressing mode1 m0 = 0: com/seg output pattern a, m0 = 1: com/seg output pattern b m1 = 0: 1 line 16 characters, m1 = 1: 2 line 8 characters bf = 1: syste m is in operation bf = 0: system is ready
16com/40seg dot matr ix lcd controller & driver S6A0072 13 contents test mode rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 0 after setting the dl bit to 4 - bit data interface mode (dl = 0), writing this code twice makes the system go to test mode. and when 8 - bit interface mode (dl = 1) is set, normal function mode is returned. system is unaffected if this code is set in 8 - bit interface, other than consuming some time. (37 m s at fosc = 270khz) clear display rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 1 clear all the display data by writing "20h" (space code of cgrom) to all ddram address, and set ddram address to "00h" into ac (address counter). for this instr uction, the cgrom address "20h" has to be set to space code. shifting of the display position returns it to the original position. namely, when display data is shifted and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. it makes entry mode to increment (i/d = 1) return home rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 1 * set ddram address to "00h" into the address counter. shifting of the display position returns it to the original position. when cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. the data in ddram does not change. entry mode set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 1 i/d s set the moving direction of cursor and displa y. i/d: increment/decrement of ddram/cgram address (cursor or blink) when i/d = "high", cursor/blink moves to right and ddram address is increased by 1. when i/d = "low", cursor/blink moves to left and ddram address is decreased by 1. s: shift of enti re display when ddram read (cgram read/write)operation or s = "low", entire display is not shift. if s = "high", and ddram write operation, entire display is shifted according to i/d value (i/d = "1": shift left, i/d = "0": shift right).
S6A0072 16com/40seg dot m atrix lcd controller & driver 14 display on/of f control rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 1 d c b control display/cursor/blink on/off 1 bit register. d: display on/off control bit when d = "high", entire display is turned on. when d = "low", entire display is turned off, but dis play data is remains in ddram. c: cursor on/off control bit when c = "high", cursor is turned on. when c = "low", cursor is disappeared in current display, but i/d register preserves its data. b: cursor blink on/off control bit when b = "high", curso r blink is on, performs alternately between all high data (black pattern) and display character at the cursor position. when b = "low", blink is off. cursor or display shift rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 1 s/c r/l * * without writin g or reading of display data, shift right/left the cursor position or display. this instruction is used to correct or search display data. (refer to table 4) during 2 - line mode display, cursor moves to the 2nd line after 8th digit of 1st line. note that di splay shift is performed simultaneously in all the line. when displayed data is shifted repeatedly, each line is shifted individually. when display shift is performed, the contents of address counter are not changed. table 4. shift patterns according to s/ c and r/l bits r/c r/l operation 0 0 shift cursor to the left, ac is decreased by 1 0 1 shift cursor to the right, ac is increased by 1 1 0 shift all the display to the left, cursor moves according to the display 1 1 shift all the display to the right, cursor moves according to the display
16com/40seg dot matr ix lcd controller & driver S6A0072 15 function set rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 dl a * m1 m0 dl: interface data length control bit when dl = "high" 8 - bit bus mode with mpu. when dl = "low", 4 - bit bus mode with mpu. thus, dl i s a signal to select 8 - bit or 4 - bit bus mode. in 4 - bit bus mode, the 4 - bit data is transferred twice. a: set the display data addressing mode when a = "low", ddram addressing mode 0. when a = "high", ddram addressing mode 1. mo: set com/s eg output rotation when m0 = "low", com/seg output rotation mode a. when m0 = "high", com/seg output rotation mode b. m1: set display line and character mode when m1 = "low", 1 line 16 character display mode. when m1 = "high", 2line 8 character displa y mode. (refer to application information) set cgram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 * ac4 ac3 ac2 ac1 ac0 msb lsb set cgram address to ac. this instruction allows the mpu to access cgram data for user defined character pa ttern. available cgram address is lower 5 bits (db4 - db0). set ddram address rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 set ddram address to ac. this instruction allows the mpu to access ddram data. when ddram addressing mo de 1 (a = 0), ddram address is from "00h" - "0fh". in ddram addressing mode 2 (a = 1), ddram address range of the 1st 8 character is "00h" - "07h", and ddram address range of the 2nd 8 character is "40h" - "47h".
S6A0072 16com/40seg dot m atrix lcd controller & driver 16 read busy flag & address ddram r s r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 bf ac6 ac5 ac4 ac3 ac2 ac1 ac0 msb lsb cgram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 0 0 bf * * ac4 ac3 ac2 ac1 ac0 msb lsb this instruction shows whether S6A0072 is in internal oper ation or not. if the resultant bf is high, the internal oper ation is in progress and should wait until bf to be low, which by then the next instruction can be performed. in the instruction you can read also the value of address counter. write data to ram write binary 8/5 bit data to ddram/cgram. the selection of ram from ddram/cgram is set by the previous address set instruction (ddram address set, cgram address set). after writing operation, the address is automatically increased/decreased by 1, according to the entry mode. read data from ram ddram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 msb lsb cgram rs r/w db7 db6 db5 db4 db3 db2 db1 db0 1 0 * * * d4 d3 d2 d1 d0 msb lsb
16com/40seg dot matr ix lcd controller & driver S6A0072 17 read binary 8/ 5 bit from ddram/cgr am the selection of ram is set by the previous address set instruction. if the address set instruction of ram is not performed before this instruction, data that was read first becomes invalid, as the direction of ac is not determined. if ram data is read several times without ram address set instruction before read operation, the cor rect ram data can be detained from the second, but the first data would be incorrect, as there is no time margin to transfer the ram data. in case of ddra m reading operation, the cursor shift instruction plays the same role as ddram address set instruction also transfers ram data to output data register. after read operation address counter is automatically increased/decreased by 1 according to the entry mo de. after cgram read operation, the display shift may not be executed correctly. - in the case of ram write operation, ac is increased/decreased by 1 like read operation (after this operation). in this time, ac indicates the next address position, but on ly the previous data can be read by read instruction.
S6A0072 16com/40seg dot m atrix lcd controller & driver 18 interface with mpu interface with 8 - bit mpu with 8 - bit interfacing data length transfer is performed at a time through 8 ports, from db0 - db7. example of timing sequence is shown below. rs r/w e internal signal db7 data busy busy no bus y data internal operation instruction busy flag check busy flag check busy flag check instruction figure 1. example of 8 - bit bus mode timing diagram interface with 4 - bit mpu when interfacing data length are 4 - bit, only 4 ports, from db4 - db7, are used as data bus. at first higher 4 - bit (in case of 8 - bit bus mode, the contents of db4 - db 7) are transferred, then the lower 4 - bit (in case of 8 - bit bus mode, the contents of db0 - db3) are transferred. so transfer is performed twice. busy flag outputs "high" after the second transfer are ended. example of timing sequence is shown below. rs r/w e internal signal db7 d7 busy no bus y d7 internal operation instruction busy flag check busy flag check instruction d3 ac3 d3 ac3 figure 2. example of 4 - bit bus mode timing diagram
16com/40seg dot matr ix lcd controller & driver S6A0072 19 application informat ion com/seg output rotat ion mode a ddram address mode 0 (a = 0) s21 s21 S6A0072 bottom view s1 s40 s20 s1 s40 s20 s1 s20 c8 c1 c16 c9 s21 s40 (m0 = 0, m1 = 0) seg1 seg20 seg21 seg40 seg41 seg60 seg61 seg80
S6A0072 16com/40seg dot m atrix lcd controller & driver 20 ddram address mode 1 (a = 1) s40 S6A0072 bottom view s1 s21 s20 s1 s20 c8 c1 c16 c9 s21 s40 (m0 = 0, m1 = 1) seg1 seg20 seg21 seg40 seg41 seg60 seg80 seg61
16com/40seg dot matr ix lcd controller & driver S6A0072 21 com/seg outpu t rotation mode b ddram address mode 0 (a = 0) s20 s20 S6A0072 top view s40 s1 s21 s40 s1 s21 s40 s21 c16 c9 c8 c1 s20 s1 (m0 = 1, m1 = 0) seg1 seg20 seg21 seg40 seg41 seg60 seg61 seg80
S6A0072 16com/40seg dot m atrix lcd controller & driver 22 ddram address mode 1 (a = 1) s1 S6A0072 top view s40 s20 s21 s40 s21 c16 c9 c8 c1 s20 s1 (m0 = 1, m1 = 1) seg1 seg20 seg21 seg40 seg41 seg60 seg80 seg61
16com/40seg dot matr ix lcd controller & driver S6A0072 23 power supply for driving lcd panel S6A0072 v2 v3 vdd v1 v4 v5 r r r r r r = 1.5k w (typ) 30%
S6A0072 16com/40seg dot m atrix lcd controller & driver 24 initializing initialize by intern al power - on - reset ci rcui t when the power is turned on, S6A0072 is initialized automatically by power on reset circuit. during the i nitialization, the following instructions are executed, and bf (busy flag) is kept "high" (busy state) up to the end of initialization. initialize f low display clear write "20h" to all ddram set functions dl = 1: 8 - bit bus mode a = 0: ddram addressing mode 0 m0 = 0: com/seg output rotation mode a m1 = 0: 1 line 16 character display mode control display on/off instruction d = 0: display off c = 0: cur sor off b = 0: blink off set entry mode i/d = 1: increment by 1 s = 0: no entire display shift initialize by extern al hardware reset if the "low" signal is forced to reset terminal over a period of 1.2 ms then system will be initialized. and bf (busy flag) is kept "high" (busy state) for 629 us after releasing the initializing sequence.
16com/40seg dot matr ix lcd controller & driver S6A0072 25 initializing by inst ruction 8 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set 0 0 0 0 1 dl(1) a * m1 m2 wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control 0 0 0 0 0 0 1 d c b wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 clear display 0 0 0 0 0 0 0 0 0 1 wait for more than 631us rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set 0 0 0 0 0 0 0 1 i/d s initialization end d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode s 0 1 entire shift off entire shift on condition: fosc = 270khz m0 0 1 com/seg output rotation mode a m1 0 1 1-line 16 character display mode a 0 1 ddram addressing mode 0 ddram addressing mode 1 dl 0 1 4-bit interface 8-bit interface com/seg output rotation mode b 2-line 8 character display mode
S6A0072 16com/40seg dot m atrix lcd controller & driver 26 4 - bit interface mode power on wait for more than 20ms after v dd rises to 4.5v wait for more than 30ms after v dd rises to 2.7v rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set (display mode set) 0 0 0 0 1 0 x x x x wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display on/off control wait for more than 39 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 display clear wait for more than 631 m s rs r/w db7 db6 db5 db4 db3 db2 db1 db0 entry mode set initialization end m1 0 1 m0 0 1 d 0 1 display off display on c 0 1 cursor off cursor on b 0 1 blink off blink on i/d 0 1 decrement mode increment mode s 0 1 entire shift off entire shift on 0 0 a * m1 m0 x x x x 0 0 0 0 0 0 x x x x 0 0 1 d c b x x x x 0 0 0 0 0 0 x x x x 0 0 0 1 i/d s x x x x 0 0 0 0 0 0 x x x x 0 0 0 0 0 1 x x x x condition: fosc = 270khz rs r/w db7 db6 db5 db4 db3 db2 db1 db0 function set (4-bit mode change) 0 0 0 0 1 dl(0) x x x x wait for more than 39 m s x: open *: don't care a 0 1 dl 0 1 4-bit interface 8-bit interface com/seg output rotation mode a 1-line 16 character display mode ddram addressing mode 0 ddram addressing mode 1 com/seg output rotation mode b 2-line 8 character display mode
16com/40seg dot matr ix lcd controller & driver S6A0072 27 frame frequency 1/16 duty cycle ... ... 16 15 3 2 1 16 15 4 3 2 1 1-line selection period vcc v1 v4 v5 . . com1 1 frame 1 frame 1 - line selection period = 160 clocks one frame = 40 x 16 x 3.7 m s x 4 = 9.472ms (1 clock = 3.7 m s at fosc = 270khz) frame frequency = 1/9.472ms = 105.6hz
S6A0072 16com/40seg dot m atrix lcd controller & driver 28 maximum absolute lim it maximum absolute pow er ratings characteristic symbol value unit p ower supply voltage (1) v dd - 0.3 to +7.0 v power supply voltage (2) v lcd - 0.3 to +13 v input voltage v in - 0.3 to v dd +0.3 v voltage greater than above may damage to the circuit (v dd 3 v2 3 v3 3 v5, v lcd = v dd - v5) temperature characte ristics characteristic symbol value unit operating temperature t opr - 30 to +85 c storage temperature t stg - 55 to +125 c
16com/40seg dot matr ix lcd controller & driver S6A0072 29 electrical character istics dc characteristics table 5. dc characte ristics (v dd = 4.5 to 5.5v, t a = - 30 to +85 c) characteristic symbol condition min typ max unit operating voltage v dd - 4.5 - 5.5 v supply current i dd internal oscillation (v dd = 5.0v, fosc = 270khz) - 1.5 1.8 ma input voltage (1) (except extclk) v ih1 - 0.7v dd - v dd v v il1 - - 0.3 - 0.8 input voltage (2) (extclk) v ih2 - v dd - 1.0 - v dd v v il2 - - 0.2 - 1.0 input voltage (3) (e pin) v ih3 - 0.8v dd - v dd v v il3 - - - 0.2v dd output voltage (1) (db0 - db7) v oh1 i oh = - 0.205(ma) 2.4 - - v v ol1 i ol = 1.6(ma) - - 0.4 voltage drop vd com i o = 0.1(ma) - - 1 v vd seg - - 1 input leakage current i il v in = 0v - v dd - 1 - 1 m a low input current i in v in = 0v, v dd = 5v (pull up) - 50 - 125 - 250 lcd driving voltage v2 v dd = 5v, v5 = 0v seg output port 2.7 3.0 3.3 v v3 1.7 2.0 2.3 divide resistor r b v dd - v5 = 5v r b = (v dd - v5)/i b i b = divi de resistor current 3.7 7.5 11.5 k w internal clock (internal rf) f ic v dd = 5v 190 270 350 khz lcd driving voltage v lcd v dd ? v 5 3.0 - 11.0 v
S6A0072 16com/40seg dot m atrix lcd controller & driver 30 (v dd = 2 . 7 to 4 .5v, t a = - 30 to +85 c) characteri stic symbol condition min typ max unit operating voltage v dd - 2 . 7 - 4 .5 v supply current i dd internal oscillation (v dd = 3 .0v, fosc = 270khz) - 0 .5 1 . 2 ma input voltage (1) (except extclk) v ih1 - 0.7v dd - v dd v v il1 - - 0.3 - 0.4 input voltage (2) ( extclk) v ih2 - v dd - 1.0 - v dd v v il2 - - 0.2 - 0 .2 v dd input voltage (3) (e pin) v ih3 - 0.8v dd - v dd v v il3 - - - 0. 4 output voltage (1) (db0 - db7) v oh1 i oh = - 0. 1 (ma) 0 . 75 v dd - - v v ol1 i ol = 0 . 1 (ma) - - 0 .2 v dd voltage drop vd com i o = 0.1(ma) - - 1 v vd seg v lcd = 5v - - 1 input leakage current i il v in = 0v - v dd - 1 - 1 m a low input current i in v in = 0v, v dd = 3 v (pull up) - 1 0 - 5 0 - 1 20 lcd driving voltage v2 v dd = 3 v, v5 = - 2 v seg output port 0 .7 1 .0 1 .3 v v3 - 0 . 3 0 0 .3 divide resistor r b v dd - v5 = 5v r b = (v dd - v5)/i b i b = divide resistor current 3.7 7.5 11.5 k w internal clock (internal rf) f ic v dd = 5v 190 270 350 khz lcd driving voltage v lcd v dd ? v 5 3.0 - 11.0 v
16com/40seg dot matr ix lcd controller & driver S6A0072 31 ac characteristics table 6. ac characteristics (vdd = 4.5 to 5.5v, t a = - 30 to +85 c) mode item symbol min typ max unit write mode e cycle time tc, 500 - - ns (refer to figure 3) e rise/fall time tr, tf - - 20 e pulse width (high, low) tw 230 - - r/w and rs setup time tsu1 40 - - r/w and rs hold time th1 10 - - data setup time tsu2 80 - - data hold time th2 10 - - read mode e cycle time tc 500 - - ns (refer to figure 4) e ri se/fall time tr, tf - - 20 e pulse width (high, low) tw 230 - - r/w and rs setup time tsu 40 - - r/w and rs hold time th 10 - - data output delay time t d - - 120 data hold time t dh 20 - - table 6. ac characteristics (vdd = 2 . 7 to 4 .5v, t a = - 30 to +85 c) mode item symbol min typ max unit write mode e cycle time tc, 1000 - - ns (refer to figure 3) e rise/fall time tr, tf - - 25 e pulse width (high, low) tw 450 - - r/w and rs setup time tsu1 60 - - r/w and rs hold time th1 20 - - data setup time tsu2 195 - - data hold time th2 10 - - read mode e cycle time tc 1000 - - ns (refer to figure 4) e rise/fall time tr, tf - - 25 e pulse width (high, low) tw 450 - - r/w and rs setup time tsu 6 0 - - r/w and rs hold time th 20 - - data output delay time t d - - 360 data hold time t dh 5 - -
S6A0072 16com/40seg dot m atrix lcd controller & driver 32 v ih1 v il1 t su1 v il1 t h1 v il1 t h1 t f t w t h2 v ih1 v il1 t su2 t r v ih1 v il1 valid data v ih1 v il1 t c db0 - db7 e r/w rs v il1 v ih1 v il1 figure 3. write mode timing diagram v ih1 v il1 t su v ih1 t h v ih1 t h t f t w t dh v ih1 v il1 t r v oh1 v ol1 valid data v oh1 v ol1 t c db0 - db7 e r/w rs t d v il1 v ih1 v il1 figure 4. read mode timing diagram

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